Project Overview

SMART LEES working to commercialize its proprietary CMOS + III-V integration platform to create novel lighting and communications silicon-based integrated circuits that take advantage of superior optoelectronic and analog/RF properties of III-V materials and devices. We invite candidates to help participate in this exciting goal.

Job Responsibilities

The Research Engineer will work with LEES’ engineered substrate development team to improve the yield and robustness of the engineered substrate manufacturing process pioneered by LEES. The candidate will be responsible for gathering and analyzing data on the engineered substrate manufacturing process, and conceiving and testing process improvements that can be transferred to external manufacturing environments in future commercialization efforts.

Job Requirements

• A Diploma or Bachelor/Master degree in Electronic/Electrical Engineering, Materials Science and Engineering, or any related discipline.
• Relevant experience in the semiconductor area (e.g. working in cleanrooms, handling semiconductor wafers/components etc.) is required, including experience in wafer bonding.
• Familiarity with materials characterization techniques is advantageous.
• Knowledge of process/quality improvement methodologies (e.g. Six Sigma) is preferred.
• The candidate needs to work well in a team, and with other lab/cleanroom users.
• The candidate should expect to complete tasks and deliver results within provided timelines, to ensure that other program goals are not delayed.

Interested applicants are invited to send in their full CV/resume, cover letter and list of three references (to include reference names and contact information). We regret that only shortlisted candidates will be notified.